Integrated circuit chips (ICs) include cells, such as transistors, capacitors and other devices grouped into plural modules to perform specific logic and arithmetic functions, such as comparators, adders, inverters and other functions. The modules are represented as standard designs in technology-specific circuit libraries, and the IC is constructed using selected modules and millions of cells. One such circuit used in IC chips is one that identifies the minimum or maximum binary value on a wire of a wire array. It is important for some operations to know the maximum or minimum binary value appearing on a wire of a wire array at a given clock cycle.
Consider an RLT-Verilog description of a circuit module that identifies a minimum value on an a-bit wide wire, W_S, of an 8-wire array, and supplies an output, Z, that represents the minimum binary value carried on a wire, as follows:    Input[2:0] W_1,W_1,W_3,W_4,W_5,W_6,W_7,W_8;    Output[2:0] Z;    /*    * [Here, the module is described in a gate level    * implementation in terms of Verilog primitives,    * AND, OR and NOT.]    */    endmodule.It would be useful to certain operations carried out by the chip to identify the minimum (or maximum) value carried by a wire W_s at a given clock period.
Timing parameters of a circuit play an important role in the synthesis of the IC design. Typically, circuits for identifying the maximum of minimum binary value on a wire of a wire array require a tree of a-bit comparators. One characteristic of the tree is its depth as a function of its input parameters. The depth of the tree is the length of the maximal path between its root and its leaves. The depth of the tree is equal to the number of levels in the tree minus one. In the case of a tree of comparators, the depth of the tree increases with each bit in the wire widths and also, possibly, with the number of wires in the array. Since the time required by the circuit to complete an operation is directly related to the depth of the circuit, each bit of the wire width in a wire array, along with the number of wires in the wire array, increases the time required for the tree to complete its operation. Consequently, there is a need for a circuit and process to calculate the minimum (or maximum) binary value on an a-bit wire of a set S of wires with possibly minimum depth.